LOW-NOISE MOS TRANSISTORS AND CORRESPONDING CIRCUIT
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jul 6, 2017
app pub date -
Apr 25, 2016
filing date -
Dec 30, 2015
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
An integrated circuit includes a MOS transistor situated in and on an active region of a semiconductor substrate. The active region is bounded by an insulating region for example of the shallow trench isolation type. The drain region of the transistor is positioned in the semiconductor substrate situated away from the insulating region. An insulated gate of the transistor includes a central opening that is positioned in alignment with the drain region. A channel region of the transistor is annularly surrounds the drain region.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully