Method for producing low-permittivity spacers
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United States of America Patent
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May 19, 2020
Grant Date -
Jun 29, 2017
app pub date -
Dec 23, 2016
filing date -
Dec 23, 2015
priority date (Note) -
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Abstract
There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.
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