MANAGEMENT OF ASYNCHRONOUS INTERRUPTS IN A TRANSACTIONAL MEMORY MULTIPROCESSOR ENVIRONMENT
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United States of America Patent
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Issued Date -
Jun 22, 2017
app pub date -
Dec 18, 2015
filing date -
Dec 18, 2015
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Abstract
A list of instructions is received. The list of instructions includes two or more instructions. Processing of all interrupts is assigned to one core of multiple cores of at least one processor. Processing of the list of instructions is assigned to the remaining cores of the multiple cores. The remaining cores of the multiple cores do not include the first core of the multiple cores. One or more of the instructions of the list of instructions are processed with the remaining cores of the multiple cores.
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