WIRING SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE, AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Jun 15, 2017
app pub date -
Dec 1, 2016
filing date -
Dec 11, 2015
priority date (Note) -
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Abstract
Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.
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