LOW RESISTANCE POWER HEADER WITH REDUCED INSTANTANEOUS VOLTAGE DROP
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United States of America Patent
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Issued Date -
Jun 8, 2017
app pub date -
Apr 11, 2016
filing date -
Dec 2, 2015
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Abstract
A power header includes a first line, and a first power-enable control device that comprises a source region and a drain region. The drain region of the first power-enable control device is coupled to the first line through a silicon-only connection, and the source region of the first power-enable control device being coupled to a power supply. In one embodiment, the first line may be coupled to a logic circuit through a silicon-only connection. In another embodiment, the first line may be coupled to a buffer circuit through a silicon-only connection. In still another embodiment, the first line may be coupled to a static random access memory cell precharge circuit.
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