INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED SILICON-GERMANIUM PFET IMPLEMENTED IN FINFET TECHNOLOGY

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United States of America Patent

SERIAL NO

15432492

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Abstract

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A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

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Patent Owner(s)

Patent OwnerAddress
STMICROELECTRONICS INCCOPPELL TX

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Liu, Qing Irvine, US 537 5415
Morin, Pierre Grenoble, FR 73 903

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