Method and System For Adaptively Adjusting a Verify Voltage to Reduce Storage Raw Bit Error Rate
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United States of America Patent
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May 25, 2017
app pub date -
Jun 17, 2016
filing date -
Nov 25, 2015
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Abstract
The various implementations described herein include systems, methods and/or devices used to enable adaptive verify voltage adjustment in memory devices. The method includes: (1) in conjunction with decoding data read from non-volatile memory in the non-volatile memory system, determining a plurality of error parameters, (2) determining, in accordance with the plurality of error parameters, a verify adjustment signal, (3) determining whether a verify trigger event has occurred, (4) in accordance with a determination that a verify trigger event has occurred, adjusting a verify voltage in accordance with the verify adjustment signal, and (5) performing data write operations to write data to non-volatile memory in the non-volatile memory system using the adjusted verify voltage to verify the data written using the data write operations.
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