MULTIPLE OPERATION INTERFACE TO SHARED COPROCESSOR
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United States of America Patent
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app pub date -
Nov 19, 2015
filing date -
Nov 19, 2015
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Abstract
In a multi-processor architecture, a plurality of processors share a coprocessor for certain instructions. Each processor may supply the coprocessor with a number of instructions and operands for those instructions. Other operations may be performed while waiting for the results. When the results are needed, the processor may be configured to force synchronization by suspending operations until the results are received. While waiting for the results, the processor enters a low-power state, waking up automatically when the last result waited upon is received.
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