ASYMMETRIC MEMORY
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United States of America Patent
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Issued Date -
May 18, 2017
app pub date -
Nov 17, 2015
filing date -
Nov 17, 2015
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Abstract
A computing system includes a central processing unit (CPU) connected to communicate over a bus, a memory configured to have at least three accessible memory storage areas arranged asymmetrically and a memory protection unit (MPU) that receives and controls memory access requests received from the central processing unit and from other processing devices, blocks or processes. The MPU determines, based on an identity of the device, block or process that generated the memory access request, whether to allow access based upon which memory area is being accessed and a type of access being requested. The areas of memory include read/write for secure and non-secure, read/write for secure only, and read for secure and non-secure but write only for secure.
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