Reduced Dissipation Switch FET Gate Biasing
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United States of America Patent
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Issued Date -
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app pub date -
Oct 10, 2016
filing date -
Oct 14, 2015
priority date (Note) -
Abandoned
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Abstract
Systems, methods, and apparatus for biasing transistors of a transistor stack are described. Such biasing can provide reduced RF power dissipation in a corresponding biasing circuit, improved safe low-frequency operation of the transistor stack while maintain a desired switching speed of the transistor stack. Such transistor stack can be used either in a shunted configuration or in a series configuration with the same benefit of reduction in dissipated RF power. Various RF switch configurations using such transistor stacks are also described.
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Patent Citation Ranking
- 11 Citation Count
- H03K Class
- 83.18 % this patent is cited more than
- 8 Age