HIGH VOLTAGE TRANSISTOR WITH SHORTENED GATE DIELECTRIC LAYER
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app pub date -
Nov 2, 2015
filing date -
Nov 2, 2015
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Abstract
A high voltage transistor includes a substrate, a well which is disposed within the substrate, a gate disposed on the well, a gate dielectric layer disposed between the well and the gate, two drift regions respectively disposed in the well at two sides of the gate, two source/drain regions respectively disposed within each drift region, wherein a width of the gate dielectric layer is smaller than a width of the source/drain region, and two isolation elements respectively disposed within each drift region
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