Processors Supporting Endian Agnostic SIMD Instructions and Methods
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United States of America Patent
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Nov 3, 2015
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Nov 3, 2015
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A processor includes a register and a load store unit (LSU). The LSU loads data into the register from a memory. When in little endian mode, bytes from sequentially increasing memory addresses are loaded in order of corresponding sequentially increasing byte memory addresses from a first end (right end) of the register to a second end (left end) of the register. When in big endian mode, bytes from sequentially increasing memory addresses are loaded in order of corresponding sequentially increasing memory addresses from the second end (left end) of the register to the first end (right) of the register. Therefore, regardless of operating in little or big endian mode, the data in the register has its most significant byte on its left side and its least significant byte on its right side which simplifies the execution of SIMD instructions because the data is aligned the same for both endian modes.
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