Resistive Random Access Memory
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United States of America Patent
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Issued Date -
Apr 27, 2017
app pub date -
Dec 3, 2015
filing date -
Oct 26, 2015
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Abstract
A resistive random access memory does not encounter the undesired effects caused by sneak current which occurs when a conventional resistive random access memory operates in an integrated circuit. The resistive random access memory includes a first electrode layer, a first insulating layer, an oxygen-containing layer, a second insulating layer and a second electrode layer. The first insulating layer is arranged on the first electrode layer. The oxygen-containing layer is arranged on the first insulating layer and includes an oxide doped with a metal element. The metal element does not exceed 10% of the oxygen-containing layer. The second insulating layer is arranged on the oxygen-containing layer, and the second electrode layer is arranged on the second insulating layer. In this arrangement, the undesired effects caused by sneak current can be effectively eliminated.
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