ONE-TIME PROGRAMMABLE MEMORY CELL CAPABLE OF REDUCING LEAKAGE CURRENT AND PREVENTING SLOW BIT RESPONSE, AND METHOD FOR PROGRAMMING A MEMORY ARRAY COMPRISING THE SAME
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United States of America Patent
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Jan 6, 2017
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May 16, 2013
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Abstract
A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.
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