TOP PINNED SOT-MRAM ARCHITECTURE WITH IN-STACK SELECTOR
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United States of America Patent
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Apr 27, 2017
app pub date -
Oct 21, 2015
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Oct 21, 2015
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Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM cell and chip architecture. The SOT-MRAM chip architecture includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells. Each memory cell of the plurality of memory cells includes a MTJ and a selector element. These SOT-MRAM cells eliminate the need to pass large currents through the barrier layer of the MTJ and the selector element eliminates the large transistors usually required for selecting a single memory cell without disturbing neighboring memory cells.
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