Distributed on-chip decoupling apparatus and method using package interconnect
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 16, 2018
Issued Date -
N/A
app pub date -
Oct 3, 2016
filing date -
May 29, 2012
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2016 Application Filing Year
- H01L Class
- 27971 Applications Filed
- 23507 Patents Issued To-Date
- 84.05 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 16, 2025 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 16, 2029 |
