CONTACTING NANO-IMPRINTED CROSS-POINT ARRAYS TO A SUBSTRATE
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United States of America Patent
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Issued Date -
Mar 30, 2017
app pub date -
Sep 29, 2015
filing date -
Sep 29, 2015
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Abstract
Embodiments of the present disclosure generally relate to memory devices having nano-imprinted patterns interconnected to conventionally processed circuitry and a method of fabrication thereof. The memory device includes a plurality of conductive traces, a substrate having a plurality of conductive pads and a plurality of conductive posts. Each conductive pad is sized to account for alignment error inherent in the nano-imprinting process. Each conductive post is coupled between a conductive trace and a conductive pad allowing interconnection of the very finely sized features of nano-imprint lithography to the larger features of a conventionally patterned wafer.
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