Reduction of Area and Power for Sense Amplifier in Memory
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United States of America Patent
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Sep 26, 2016
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Sep 24, 2015
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Abstract
The present invention is directed to a memory subsystem including a plurality of memory banks, each of the memory banks including a plurality of memory cells arranged in rows and columns with word-lines connecting to the memory cells along a row direction and bit-lines connecting to the memory cells along a column direction; a sense amplifier module shared by the plurality of memory banks, the sense amplifier module including a plurality of sense amplifiers for sensing resistance of the memory cells; a plurality of memory buffer modules coupled to the sense amplifier module, each of the memory buffer modules including a plurality of memory buffers for storing data from the sense amplifiers; and an input/output (I/O) interface coupled to the memory buffer modules.
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