Memory device which performs verify operations using different sense node pre-charge voltages and a common discharge period
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United States of America Patent
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Aug 1, 2017
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Mar 16, 2017
app pub date -
Sep 10, 2015
filing date -
Sep 10, 2015
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Abstract
Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. During sensing of first and second memory cells, a control circuit pre-charges first and second sense circuits to first and second voltages, respectively. The first and second sense circuits are associated with the first and second memory cells, respectively. Also, during the sensing, a control gate voltage is applied to the first and second memory cells. The control circuit allows the first and second sense node voltages to discharge in a common discharge period and the cells are sensed using a common trip condition. The first and second memory cells are therefore subject to different concurrent verify tests.
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