Synchronising devices using clock signal delay comparison
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United States of America Patent
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Jun 9, 2020
Grant Date -
Mar 9, 2017
app pub date -
Sep 9, 2016
filing date -
Sep 9, 2015
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Abstract
A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.
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