INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SINGLE-LAYER SUPPORT STRUCTURE

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20170069565A1
SERIAL NO

15257770

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Approaches, techniques, and mechanisms are disclosed for a method of manufacturing an integrated circuit package with a single-layer substrate. In an embodiment, the inventive integrated circuit package not only reduces manufacture cost but also improves reliability and miniaturization. According to an embodiment, a single-layer substrate is manufactured using non-photoimageable dielectric (NPID) material that is different from other dielectric materials, such as PrePreg (PPG) materials, copper clad laminates (CCL), solder resists (SR), and so forth, that are used in conventional substrates. A single-layer substrate manufactured using the NPID material provides a low cost solution by, among other aspects, eliminating certain process steps, such as a laser drill process, that are often used to manufacture the other substrates. According to an embodiment, the NPID material utilized for the described techniques and systems may feature a low coefficient of thermal expansion (CTE), a high glass transition temperature (Tg), and/or a high modulus compared to the other dielectric materials. Such features improve reliability because of, among other aspects, improved trace protection and peel strength, thereby enhancing adhesion between traces (e.g., of copper (Cu), etc.) and dielectric materials. In an embodiment, such features also improve miniaturization because, for example, the NPID material may allow formation of traces with reduced geometry.

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Patent Owner(s)

Patent OwnerAddress
STATS CHIPPAC PTE LTD5 YISHUN STREET 23 SINGAPORE 768442

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHOI, BONG WOO Seoul, KR 7 1
JANG, JIWON SEOUL, KR 5 2
KIM, SUNGSOO Seoul, KR 101 963
PARK, HYUNGSANG Gyeonggi-do, KR 14 128

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