Low resistance contact interlayer for semiconductor devices

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10833187
APP PUB NO 20170040463A1
SERIAL NO

14821330

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Abstract

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A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONNEW ORCHARD ROAD ARMONK NY 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Jeehwan Los Angeles, US 249 1355
Liu, Wencong Shandong, CN 3 5
Sadana, Devendra K Pleasantville, US 897 10959

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