Select Gates with Conductive Strips on Sides
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United States of America Patent
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Issued Date -
Jan 26, 2017
app pub date -
Jul 24, 2015
filing date -
Jul 24, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A NAND flash memory array includes a select line that is formed from a portion of a first conductive layer and a portion of second conductive layer separated by dielectric, and a connecting portion of a third conductive layer, the connecting portion extending in contact with a side of the portion of the first conductive layer and a side of the portion of the second conductive layer
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