NON-VOLATILE MEMORY DEVICE FOR REDUCING BIT LINE RECOVERY TIME
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United States of America Patent
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Issued Date -
Jan 26, 2017
app pub date -
Jul 24, 2015
filing date -
Jul 24, 2015
priority date (Note) -
Published
status (Latency Note)
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Abstract
Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.
First Claim
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