On-chip training of memristor crossbar neuromorphic processing systems
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United States of America Patent
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Jan 5, 2021
Grant Date -
Jan 12, 2017
app pub date -
Jul 6, 2016
filing date -
Jul 6, 2015
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Abstract
An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.
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