INTEGRATED ESD PROTECTION CIRCUITS IN GAN
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United States of America Patent
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Issued Date -
Dec 22, 2016
app pub date -
Jun 18, 2015
filing date -
Jun 18, 2015
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Abstract
An electronic circuit is disclosed and described herein. The circuit includes first and second pins, and an overvoltage protection circuit including a first enhancement-mode transistor. The overvoltage protection circuit is disposed on a GaN-based substrate, and the first enhancement mode transistor is configured to provide overvoltage protection between the first and second pins.
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