High Voltage Vertical FPMOS Fets
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United States of America Patent
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Issued Date -
Dec 22, 2016
app pub date -
Jun 18, 2015
filing date -
Jun 18, 2015
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Abstract
Semiconductor power devices such as vertical FPMOS are described having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches. Higher voltage resistance is achieved while increasing current by spacing the trenches and providing particular dopant levels to allow more even distribution of depletion layer regions across a power device during use.
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