GATE-ALL-AROUND VERTICAL GATE MEMORY STRUCTURES AND SEMICONDUCTOR DEVICES, AND METHODS OF FABRICATING GATE-ALL-AROUND VERTICAL GATE MEMORY STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF
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United States of America Patent
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Issued Date -
Dec 8, 2016
app pub date -
Jun 3, 2015
filing date -
Jun 3, 2015
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Abstract
Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around vertical gate semiconductor structure comprising forming a plurality of layers over a substrate, the plurality of layers having alternating first insulative material layers and conductive material layers; identifying bit line and word line locations for the formation of bit lines and word lines; removing portions of the plurality of layers outside of the identified bit line and word line locations; forming vertical second insulative material structures in areas outside of the identified bit line and word line locations; removing portions of the plurality of layers in areas along the identified word line locations outside of the identified bit line locations; removing the first insulative material from the first insulative material layers in areas along the identified word line locations; forming bit lines in the identified bit line locations; and forming word lines in the identified word line locations.
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