Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode
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United States of America Patent
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Jul 21, 2020
Grant Date -
Dec 8, 2016
app pub date -
Dec 14, 2014
filing date -
Dec 14, 2014
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Abstract
A cache stores 2{circumflex over ( )}J-byte cache lines has an array of 2{circumflex over ( )}N sets each holds tags each X bits and 2{circumflex over ( )}W ways. An input receives a Q-bit address, MA[(Q−1):0], having a tag MA[(Q−1):(Q−X)] and index MA[(Q−X−1):J]. Q is at least (N+J+X−1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2{circumflex over ( )}W ways of the selected set when operating in a first mode; and into a subset of the 2{circumflex over ( )}W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion.
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