INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATE ELECTRODES
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United States of America Patent
Stats
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N/A
Issued Date -
Dec 1, 2016
app pub date -
May 26, 2015
filing date -
May 26, 2015
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes defining a pFET region and an nFET region of a semiconductor substrate. The method deposits a first work function material including tungsten and nitride over the pFET region and the nFET region of the semiconductor substrate. The method includes selectively modifying the first work function material in a selected region. Further, the method includes depositing a metal fill over the first work function material in the pFET region and the nFET region of the semiconductor substrate.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
GLOBALFOUNDRIES INC | PO BOX 309 UGLAND HOUSE GRAND CAYMAN KY1-1104 |
International Classification(s)

- 2015 Application Filing Year
- H01L Class
- 25498 Applications Filed
- 22451 Patents Issued To-Date
- 88.06 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Patil, Suraj K | Ballston Lake, US | 24 | 154 |
# of filed Patents : 24 Total Citations : 154 | |||
Togo, Mitsuhiro | Burnt Hills, US | 35 | 215 |
# of filed Patents : 35 Total Citations : 215 |
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Patent Citation Ranking
- 10 Citation Count
- H01L Class
- 13.47 % this patent is cited more than
- 9 Age
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jun 1, 2028 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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