PROCESS FOR PRODUCING MOS TRANSISTORS HAVING A LARGER CHANNEL WIDTH FROM AN SOI AND IN PARTICULAR FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT
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United States of America Patent
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Issued Date -
Dec 1, 2016
app pub date -
Dec 8, 2015
filing date -
Dec 8, 2015
priority date (Note) -
Abandoned
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Abstract
An integrated circuit includes a substrate with an isolation region that bounds a zone. A transistor includes a concave semiconductor region that is supported by the isolation region in a first direction and has a concavity turned to face towards the zone. The concave semiconductor region contains drain, source and channel regions. A gate region for the transistor possesses a concave portion overlapping a portion of the concave semiconductor region. A dielectric region is located between the zone of the substrate and the concave semiconductor region.
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