Large-Scale Complementary Macroelectronics Using Hybrid Integration of Carbon Nanotubes and Oxide Thin-Film Transistors
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United States of America Patent
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Dec 1, 2016
app pub date -
May 27, 2016
filing date -
May 27, 2015
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Abstract
A method of fabricating a logic element, the method includes forming a p-type nanomaterial thin film transistor on a substrate, forming a n-type metal oxide thin film transistor on the substrate, and connecting the p-type nanomaterial thin film transistor to the n-type metal oxide thin film transistor to form the logic element. The logic element is a hybrid complementary logic element.
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