Dynamic cache replacement way selection based on address tag bits
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United States of America Patent
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Jun 30, 2020
Grant Date -
Dec 1, 2016
app pub date -
Dec 14, 2014
filing date -
Dec 14, 2014
priority date (Note) -
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Abstract
A cache memory comprising: a mode input indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of entries having a plurality of sets by W ways; an input receives a memory address comprising: an index used to select a set from the plurality of sets; and a tag used to compare with tags stored in the entries of the W ways of the selected set to determine whether the memory address hits or misses; and allocation logic, when the memory address misses in the array: selects one or more bits of the tag based on the allocation mode; performs a function, based on the allocation mode, on the selected bits of the tag to generate a subset of the W ways of the array; and allocates into one way of the subset of the ways of the selected set.
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