Dynamic Clock Chain Bypass
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United States of America Patent
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Issued Date -
Dec 1, 2016
app pub date -
May 26, 2015
filing date -
May 26, 2015
priority date (Note) -
Abandoned
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Abstract
An apparatus for testing an electronic circuit includes a clock scan chain input, a clock scan chain output, and a number of clock controllers connected in series in a clock scan chain between the clock scan chain input and the clock scan chain output. Each of the clock controllers includes an input, a bypass flip flop connected to the input, a number of clock control bit flip flops connected in series to an output of the bypass flip flop, a bypass multiplexer having a first input connected to an output of a last of the clock control bit flip flops and a second input connected to the output of the bypass flip flop, and a holding flip flop having an input connected to the output of the bypass flip flop and an output connected to a select input of the bypass multiplexer.
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