Transistor with threshold voltage set notch and method of fabrication thereof
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United States of America Patent
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Mar 20, 2018
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app pub date -
Jun 24, 2016
filing date -
Jun 22, 2010
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Abstract
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT (variation in VT) compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from VT for a given device.
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