MEMORY SUBSYSTEM SYNCHRONIZATION PRIMITIVES
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United States of America Patent
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Issued Date -
Nov 17, 2016
app pub date -
Sep 14, 2015
filing date -
May 11, 2015
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Abstract
An apparatus includes a first data processor configured to communicate first data and handshake information to a non-coherent memory system. The apparatus includes a second data processor coupled in a pipeline with the first data processor and configured to execute in parallel with the first data processor. The second data processor is configured to read the first data from the non-coherent memory system in response to receiving an indicator from the non-coherent memory system based on the handshake information. The apparatus may include the non-coherent memory system. The non-coherent memory system may include a memory controller configured to receive the first data and the handshake information, the memory controller being configured to provide the indicator in response to the first data being available for a read.
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