Low-power partial-parallel chien search architecture with polynomial degree reduction
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United States of America Patent
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Oct 10, 2017
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May 7, 2015
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May 7, 2015
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Abstract
A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.
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