SEMICONDUCTOR MEMORY DEVICE BIT LINE TRANSISTOR WITH DISCRETE GATE
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United States of America Patent
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Issued Date -
Oct 20, 2016
app pub date -
Apr 15, 2015
filing date -
Apr 15, 2015
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Abandoned
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Abstract
A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the diffusion regions comprise source and drain regions of a bit line transistor pair comprising a first bit line transistor and a second bit line transistor and a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs, wherein the first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region, wherein a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and the second bit line transistor of the second diffusion layer.
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