FLIP-FLOP CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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United States of America Patent
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Issued Date -
Oct 13, 2016
app pub date -
Mar 23, 2016
filing date -
Mar 23, 2016
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A flip-flop circuit includes a first gate, a first latch, a second gate, a second latch and a third gate. The first gate is configured to operate in accordance with a first edge of a clock signal, and the first latch is configured to hold an output data of the first gate. The second gate is configured to operate in accordance with a second edge of the clock signal, and the second latch is configured to hold an output data via the second gate. The third gate, which is provided between the first latch and the second latch in series with the second gate, is configured to operate in accordance with a control signal which is a delayed signal of the clock signal.
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