Wafer with plated wires and method of fabricating same
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United States of America Patent
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Nov 20, 2018
Grant Date -
Oct 13, 2016
app pub date -
Apr 8, 2015
filing date -
Apr 8, 2015
priority date (Note) -
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Abstract
An aspect of the invention includes a method for plating wires on a wafer comprising: forming an array of integrated circuit (IC) chips having a redistribution level; forming a kerf bus, the kerf bus separating each of the IC chips from each other, the kerf bus being connected to an edge of the wafer; forming an array of wires in the redistribution level of each IC chip; electrically connecting at least one wire in the array of wires on each IC chip to the kerf bus; and electroplating the array of IC chips.
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