Methods and Apparatus for Deuterium Anneal of Multi-Layered Semiconductor Structure

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United States of America Patent

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14683914

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Methods and apparatus for passivation of semiconductor interfaces by deuterium annealing are described. Harmonic improvements after deuterium annealing of a SOI semiconductor device with a trap-rich layer was demonstrated. Secondary ion mass spectroscopy after deuterium anneal shows a deuterium rich interface layer at the BOX-trap-rich layer interface of a MOSFET semiconductor device.

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PSEMI CORPORATION9369 CARROLL PARK DRIVE SAN DIEGO CA 92121

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Goktepeli, Sinan San Diego, US 89 671
Hammond, Richard Hillcrest, US 95 3215

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