Low latency digital clock fault detector
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United States of America Patent
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Jan 2, 2018
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app pub date -
Mar 9, 2016
filing date -
Apr 8, 2015
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Abstract
A low latency digital clock fault detector has an edge detector including a delay line generating pulses on edges o an incoming clock signal of a width determined by the length of said delay line. A watchdog timer with flip-flops in a pipeline configuration has a first input held at a static logic level, a second input receiving a reference clock, and a third reset input. The watchdog is being responsive to the pulses to maintain a stable output in the presence of said pulses and generate a fault indication in the absence of the pulses.
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