Packet processing system, method and device having reduced static power consumption
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United States of America Patent
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Mar 30, 2015
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Mar 30, 2015
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Abstract
A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.
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