SEMICONDUCTOR MEMORY DEVICE
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United States of America Patent
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Issued Date -
Sep 29, 2016
app pub date -
Sep 3, 2015
filing date -
Mar 26, 2015
priority date (Note) -
Abandoned
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Abstract
The semiconductor memory device of the invention includes 2 TFT MOS transistors, 2 bulk MOS transistors, a first and second access MOS transistors and a first and second capacitor. The TFT and bulk MOS transistors form a latch for retaining a data that is inverted between a first and second node. The first bulk access MOS transistor switches the first node to connect to a first bit line according to a voltage of a word line. The second bulk access MOS transistor, switches the second node to connect to a second bit line according to the voltage of the word line. The first capacitor is disposed between the first node and a power supply voltage. The second capacitor is disposed between the second node and the power supply voltage. The bulk MOS transistors and the access MOS transistors are formed by a recess gate type MOS transistor.
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