APPARATUS AND METHOD FOR GENERATING A REDUCED NUMBER OF TEST VECTORS AND INSERTING TEST POINTS FOR A LOGIC CIRCUIT
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United States of America Patent
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Sep 22, 2016
app pub date -
Mar 20, 2015
filing date -
Mar 20, 2015
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Abstract
A method is described that includes performing the following by executing program code on a computing system. Generating an expression describing the operation of an electronic circuit for each of a plurality of faults within the circuit. Generating a plurality of fault equations for each of the faults that compare output bits of a faulty circuit with output bits of a working circuit. Combining the fault equations into a conjunctive logical expression. Attempting to solve a problem posed by the conjunctive logical expression with a MAXSAT solver to generate a test vector for the electronic circuit.
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