Method and system of fast nested-loop circuit verification for process and environmental variation and hierarchical circuits
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United States of America Patent
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Jun 25, 2019
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Sep 22, 2016
app pub date -
Oct 24, 2014
filing date -
Oct 24, 2013
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Abstract
A computer-implemented method for quickly analyzing the effect of process, voltage, temperature, and other variations when the variation analysis or circuit structure can be hierarchically composed into nested loops. The method has two main steps: first, it hierarchically generates a set of points and inserts them into a flat list of tuples, where each tuple contains a point from each level in the looping hierarchy. Second, it efficiently identifies and simulates failing tuples with the assistance of modeling to order the tuples to simulate. By using the present method, a designer does not have to simulate the full ECD at each and every statistical process point or PVT corner, which can same considerable time or compute effort.
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