TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL
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United States of America Patent
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Issued Date -
Sep 15, 2016
app pub date -
Mar 10, 2015
filing date -
Mar 10, 2015
priority date (Note) -
Abandoned
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Abstract
Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.
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