Static data bus address allocation
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United States of America Patent
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Aug 23, 2022
Grant Date -
Sep 8, 2016
app pub date -
Mar 4, 2016
filing date -
Mar 6, 2015
priority date (Note) -
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Abstract
The present invention relates to a data bus node integrated circuit comprising at least one static address selection terminal and a detecting circuit for detecting a state of the address selection terminal. The IC also comprises a communication circuit for data communication over a data bus. This circuit is adapted for determining a node address identifier taking the detected state of the at least one static address selection terminal into account. The detecting circuit is adapted for detecting the state of the address selection terminal by determining whether the address selection terminal is in a floating state, a power supply voltage state or a ground voltage state.
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