MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES
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United States of America Patent
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app pub date -
May 17, 2016
filing date -
Feb 27, 2013
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Abandoned
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Abstract
A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.
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