MANAGING REUSE INFORMATION FOR MEMORY PAGES
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Mar 4, 2015
filing date -
Mar 4, 2015
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses using mappings in a first page table accessed by the guest operating system; translating from the intermediate physical addresses to physical addresses using mappings in a second page table accessed by the hypervisor; determining reuse information for a second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page; storing the determined reuse information in both the first page table and the second page table; and using the stored reuse information to store cache lines in selected portions of a first cache.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully